Abstract—In this paper, we propose an efficient VLSI architecture for variable block size motion estimation (VBSME) in H.264/AVC to reduce the hardware cost and latency. The proposed architecture adopts four modes (8x8, 8x16, 16x8 and 16x16 modes) instead of seven modes for VBSME specified in H.264/AVC. Our architecture significantly reduces the hardware size by reducing (1) the registers and adders in each processing unit, (2) the comparison elements, and (3) the registers used to store the minimum SADs and motion vectors. The experimental result shows that our proposed architecture reduces the hardware size by 44.3% while it also increases the operation clock frequency by 54.9% compared with the best-known architecture. The proposed architecture satisfied the real-time processing requirement of the massive data in high resolution video applications.

Index Terms—H264/AVC, VBSME, motion estimation, 1-D tree architecture, VLSI design, video codec

Cite: Dam. Minh Tung and Tran. Le Thang Dong, "A VLSI Architecture for H.264/AVC Variable Block Size Motion Estimation," Jounal of Automation and Control Engineering, Vol. 3, No. 1, pp. 51-55, February, 2015. doi: 10.12720/joace.3.1.51-55