Abstract—Nowadays, the number of cores in a micro-processor used for automotive embedded systems are trending to be increased from tens (multi) to hundreds (many) of cores to achieve higher performance. Developing many-core architectures with high-performance and low-power is becoming a major technical challenge. In this paper, we propose a solution to develop the many-core architecture by using many low-performance but small and very low-power cores to obtain very high performance and efficient parallel processing. The many-core evaluation platform is implemented on FPGA utilizing multiple mass-produced evaluation boards, which can result to several advantages such as low cost of development, flexibility and easy implementation as compared to that of manufacturing in a real LSI chip. In addition, some evaluation results of parallel benchmark programs conducted on our developed platform are also presented and discussed.

Index Terms—many-core architecture, evaluation platform, network-on-chip, parallel benchmark, FPGA

Cite: Trung-Dung Pham, Van-Tien Nguyen, and Truong-Son Nguyen, "Development of a Many-core Architecture for Automotive Embedded Systems," Jounal of Automation and Control Engineering, Vol. 4, No. 2, pp. 147-152, April, 2016. doi: 10.12720/joace.4.2.147-152