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IO Standard Based Low Power Design of RAM and Implementation on FPGA

Deepa Singh, Bishwajeet Pandey and Manisha Pattanaik
Atal Bihari Vajpayee-Indian Institute of Information Technology and Management, Gwalior
Abstract—In this work, we are applying different LVCMOS based IO standard in the target design and maintain same drive strength for low power design. Spartan-3 is 90-nm FPGA, on which we implement our circuit to re-assure power reduction in memory design. Here, drive strength is 8mA uniform. Power consumption is increasing with LVCMOS12 than the power consumption with LVCMO25 when frequency is higher than 1GHz. Power consumption is decreasing with LVCMOS12 than the power consumption with LVCMO25 when frequency is lower than 1GHz. 1 GHz is a threshold on which there is change in behavior of power dissipation. There is 18.81% power reduction achieved when memory is operating with 1GHz clock frequency. Current is maximum 1.681A on 1 THz and current is minimum i.e. 0.026A on 1 MHz clock frequency.

Index Terms—LVCMOS, dynamic power, IO standard, RAM, drive strength, frequency.


Cite: Deepa Singh, Bishwajeet Pandey, and Manisha Pattanaik, "IO Standard Based Low Power Design of RAM and Implementation on FPGA," Jounal of Automation and Control Engineering, Vol. 1, No. 4, pp. 316-320, Dec., 2013. doi: 10.12720/joace.1.4.316-320
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