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A High Speed-Low Power Comparator with Composite Cascode Pre-amplification for Oversampled ADCs

Kavindra Kandpal, Saloni Varshney, and Manish Goswami
Department of Microelectronics, Indian Institute of Information Technology, Allahabad, India
Abstract—This paper presents a high speed- low power CMOS comparator using composite cascode differential pair as a pre-amplification stage. The purpose of this work is to design a comparator for oversampled ADC application. This comparator is designed using 180nm CMOS technology with a power supply of 1.2V. Pre and post layout simulation of the proposed circuit is done using cadence tool. The total power consumption of the comparator is 71.61μW and unity gain-bandwidth is 1GHz. The DC offset voltage is 12mV, gain is 70dB while total area occupied by comparator is 684μm2. This design achieves an OSR (Oversampling Sampling Ratio) greater than 1000 which corresponds to SNR improvement of 30dB for Σ-Δ converters.

Index Terms—high speed comparator, analog to digital convertor, composite cascode, oversampled ratio.

Cite: Kavindra Kandpal, Saloni Varshney, and Manish Goswami, "A High Speed-Low Power Comparator with Composite Cascode Pre-amplification for Oversampled ADCs," Jounal of Automation and Control Engineering, Vol. 1, No. 4, pp. 301-305, Dec., 2013. doi: 10.12720/joace.1.4.301-305
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