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High Throughput– Resource Saving Hardware Implementation of AES-CCM for Robust Security Network

Dang Khoa Nguyen, Leonardo Lanante and Hiroshi Ochi
Dept. of Computer Science and Electronics Kyushu Institute of Technology, Iizuka, Fukuoka, Japan

AbstractThis paper presents a new architecture andASICimplementation of high throughput of Counter with Cipher Block Chaining – Message Authentication Code(CCM) for robust security network such as gigabit wireless IEEE 802.11ac in case considering trade-off between throughput and resource saving. We propose a new architecture of AES-CCM core adopted in parallel which utilizes two separated AES forward cipher cores for MIC calculation in Counter (CTR) Mode and encryption or decryption data in Cipher Block Chaining (CBC) Mode. The implementation of AES-CCM core in Synopsys CMOS SAED90nm process achieves2.69Gbps of throughput at 264MHz clock frequency.The proposed architecture of AES-CCM corereduces latencyby one AES cycle in comparison with conventional architectures. In addition,the AES-CCM core supports bothgeneration-encapsulation and decryption-verifica-tionprocess with symmetrical data processing routine. We also introduce an implementation of reordering AES transformation method comes along with composite Sbox in order to gain maximal period of the composition and saving resources compared to original AES algorithm implementation.

Index Terms—AES, AES-CCM, CCMP, WPA2, 802.11i, Security

Cite: Dang Khoa Nguyen, Leonardo Lanante and Hiroshi Ochi, "High Throughput– Resource Saving Hardware Implementation of AES-CCM for Robust Security Network," Journal of Automation and Control Engineering, Vol.1, No.3, pp. 250-254, Sep. 2013. doi: 10.12720/joace.1.3.250-254

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